The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials. The metallization patterns interconnect, hence the term “interconnects”, the electrical components to form integrated circuits. The term interconnect is defined herein to include all interconnection components including trenches and openings or vias filled with conductive material.
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a dielectric layer and the dielectric material is etched through the photoresist material patterning to form a hole or a via (hereinafter collectively referred to as “an opening” or “openings”) to form a pathway between an underlying metal and an adjacent trench or other interconnect structure. The photoresist material is removed and the opening and trench are commonly coated with a barrier and a seed layer then filled with a low resistivity metal to form a conductive pathway through the opening and trench.
Formation of the conductive pathway through high aspect openings using common barrier, seed, and trench materials can compromise continuity of the seed layer on high aspect ratio opening surfaces leading to incomplete film coverage, can increase electromigration in the openings leading to reliability failures, and can limit thickness of the dielectric layer as a result of gap-fill constraints.
Turning now to the figures, the illustration in FIG. 1 (Prior Art) is a cross-sectional view of an opening 110 formed adjacent to a trench 120 formed over and directly adjacent to the opening 110, the opening 110 having an opening width 112 and an opening height 114. A barrier 130 is formed using a physical vapor deposition (PVD) process on a trench surface 140, an opening sidewall 150, and an underlying metal surface 160. Deposition of the barrier 130 using the PVD process results in a non-conformal barrier 130 thickness along the opening sidewall 150 due to the anisotropic nature of the deposition process. The non-conformal barrier 130 in the opening 110 can result in areas with thin or missing portions of a barrier 130 along a portion of the opening sidewall 150, leaving at least a portion of the opening sidewall 150 exposed.
The barrier 130 is a multi-layer film that typically consists of a tantalum nitride (TaN) film and a tantalum (Ta) film stack that is used to minimize or substantially prevent diffusion of contaminants across the barrier 130. An underlying metal 170 of copper (Cu) is formed in the dielectric region 180 using methods known to one skilled in the art. The dielectric region 180 is selectively formed of a dielectric material to electrically isolate conductors, reduce resistance capacitance (“RC”) delay and improve device performance, such as silicon dioxide (SiO2).
FIG. 2 (Prior Art) illustrates the device in FIG. 1 after forming a conductive layer 210 on the barrier 130. The conductive layer 210 is a multi-layer film of Cu that typically consists of a seed layer comprising Cu deposited using a PVD process followed by a thicker Cu layer deposited using an electroplating process to form the conductive layer in the opening 110 and the trench 120. Deposition of the PVD seed layer can exacerbate nonconformity exhibited by the barrier 130 when forming the conductive layer 210, leading to one or more voids 220 in the opening 110. Formation of the conductive layer 210 is challenging since the seed layer must be continuously formed along the opening sidewalls 150 using a largely anisotropic process to deposit the layer along vertical or nearly vertical opening sidewalls 150, meaning that a direction rate in the direction normal to a surface is much higher than in a direction parallel to the surface. Formation of the conductive layer 210, when formed with minimal voids (not shown), creates a seam near a center of the opening 110 created when the conductive layer 210 fills the opening 110 from substantially laterally opposite sidewalls.
The opening sidewalls 150 may be tapered (not shown) to provide a more robust seed layer deposition process, however via resistance and reliability is compromised since the tapered profile increases current density near the bottom of the opening 110 as the opening thickness 112 shrinks. As a result, an aspect ratio of the opening 110, or the ratio of the opening height 114 to the opening width 112 is limited to allow filling of the opening 110 using traditional methods. Limiting the aspect ratio forces a reduction in the opening height 114 as the opening width 112 continues to shrink, while increasing capacitance. Further, deposition of the barrier 130 on the underlying metal surface 160 creates an electrical barrier that also increases resistance to electrical flow between the conductive layer 210 and the underlying metal 170.